Pattern recognition is an important function for associative addressable or content-addressable memories and neural networks. For content-addressable memories, pattern recognition has long been performed in custom integrated circuits. These circuits store data at random memory locations and provide a positive indication when an input word perfectly matches a data word stored in one of the memory locations. Digital logic has been utilized for implementations of such circuits. A review of these memories with exemplary circuits is found in Content-Addressable Memories by T. Kohonen, pages 199-203 (Springer-Verlag 1980).
In U.S. Pat. No. 4,780,845, a content-addressable memory cell is shown consisting of a dynamic random-access memory (DRAM) connected and an exclusive-NOR (XNOR) gate. For each cell, one bit of the input word is compared to the corresponding bit in the stored word via the exclusive-NOR gate to generate a match signal or non-match signal. The outputs from the exclusive-NOR gates comprising the cells grouped together to form a word within the content-addressable memory are connected to the same output bus line which is commonly called the match line. Connection of the exclusive-NOR outputs to the match line as shown in the '845 patent is a wired-OR connection. That is, if any one bit of the input word fails to match the bit in the corresponding bit position of the stored word, then the entire match fails and the match line is forced to a level signifying a non-match or match failure condition.
In general, for known content-addressable memories such as the one in the '845 patent, there is no attempt to indicate the correlation or degree of closeness for a match between the input word and stored words. That is, this content-addressable memory cell having a wired-OR match line cannot indicate that the input word, while not exactly matching a stored word, most closely matched a particular stored word.
In U.S. Pat. No. 3,633,182 and a technical article from IEEE J. Solid-State Circuits, Vol. SC-5, pp. 208-215 (1970), an alternative content-addressable memory cell is shown consisting of a static random-access memory (SRAM) or flip-flip in combination with a comparing logic gate. The operation of this content-addressable memory is substantially identical to the operation of the memory in the '845 patent described above. Each bit of the input word is compared to the bit in the corresponding position from the word stored in the associated SRAMs. The output from each associated comparing logic gate is connected to a match line. When the comparison fails in one of the comparing logic gates for a stored word, the comparing logic gate operates in a manner to force the match line to exhibit a level indicative of match failure or non-match, just as in the '845 patent described above. There is no attempt in this memory to indicate the correlation or degree of closeness for a match between the input word and the stored words. Only exact matches between the input word and a stored word can be indicated by this memory.
As this area continued to develop, it became apparent that the parallel searching architecture of the content-addressable memory would be suited for use in the parallel computing structures employed in artificial neural networks. But in pattern recognition applications, artificial neural networks attempt to measure the degree to which an input pattern matches a stored template. This task, of course, is not directly achievable with standard content-addressable memories such as those described above. To this end, large distributed computing structures built around the content-addressable memory have been proposed to handle the more complex problem of recognizing a close match or the best match rather than the exact match. In some applications, the recognition of a close match is called a "less-than" or "greater-than" match. The large distributed computing structures have been realized primarily by utilizing a bit-serial search engine in conjunction with a content-addressable memory. See descriptions of these structures in IEEE J. Solid-State Circuits, Vol. 24, No. 4,pp. 1014-20 (1989); IEEE J. Solid-State Circuits, Vol. 24, No. 4, pp. 1003-13 (1989); and IEEE J. Solid-State Circuits, Vol. 24, No. 1, pp. 28-34 (1989). Such large distributed computing structures are necessitated by the requirement of achieving high throughput for large-bit length data. It is important to note that each of the content-addressable memory cell circuits described in the articles cited directly above provide a wired-OR output to the match line so that failure to match in one bit position causes the entire match to fail and exhibit the match failure condition on the match line. As a result, the computing structures surrounding the content-addressable memory are quite large and awkward on order to achieve a certain level of artificial intelligence.